Field of the Invention
The invention relates to a trench MOS transistor having a semiconductor body of the first conduction type, in which a trench provided with a gate electrode is provided, which has at least one source zone of the first conduction type in a side area at its upper end and reaches with its lower end into the semiconductor body forming at least one drain zone of the first conduction type, a body region of the second conduction type being provided between source zone and drain zone and the gate electrode being isolated from source zone, body region and drain zone by an insulating layer which has a step, so that the insulating layer has a larger layer thickness toward the lower end of the trench than at the upper end thereof.
In the development of new generations of DMOS power transistors, an important aim is to reduce the on resistivity Ron.A (A=effective area). By satisfying such a requirement, it is possible, on one hand, to minimize the static power loss in a DMOS power transistor and, on the other hand, it is thereby possible to achieve higher current densities in the DMOS power transistor. As a result, it is possible to use smaller and less complicated chips for a configuration that processes the same total current.
It is known that the on resistivity Ron can be considerably reduced if the planar structure is departed from and a trench structure is employed. The reduction applies, in particular, to integrated configurations, in which trench cells are, therefore, preferably used instead of planar structures. The use of trench cells makes it possible, in particular, to reduce the channel resistance due to a considerable enlargement of the channel width per area.
Using deep trenches can reduce the resistance of the drift path that is preferably located in an epitaxial layer on a semiconductor substrate, the so-called xe2x80x9cepi-resistancexe2x80x9d (cf., in particular, U.S. Pat. No. 4,941,026 to Temple). However, such deep trenches presuppose a thicker insulating layer in their lower region than in the actual channel region. At the transition between the thicker and the thinner insulating layer, which preferably includes silicon dioxide, an oxide step is present that is unavoidable in deep trenches. At the oxide step, however, during off-state operation of the MOS transistor, there occur considerable spikes of the electric field in the semiconductor body directly below the step. With a small distance between adjacent trenches, these electric field spikes are higher than the values of the electric field in the cell center at the pn junction between source zone and body region. Therefore, avalanche multiplication of charge carriers and injection of hot charge carriers into the gate insulating layer can occur. As a result, the gate insulation layer is damaged and the destruction of the MOS transistor may even be brought about.
Hitherto, the consequences of such a problem, which arises specifically in MOS transistors with deep trenches, have not yet been identified.
It is accordingly an object of the invention to provide a trench MOS transistor that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and that has deep trenches in which a breakdown at the oxide step in the trench is reliably prevented.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a trench MOS transistor, including a semiconductor body with a first conductivity type, the body forming at least one drain zone with the first conductivity type, the body having a trench with a gate electrode, a trench side area, a trench upper end, and a trench lower end extending into the body, at least one source zone with the first conductivity type, the source zone disposed in the trench side area at the trench upper end and having a source lower end, a first region with a second conductivity type, and a second region with the second conductivity type, the second region buried in the first region, having a higher doping than the first region, and disposed between the source zone and the drain zone, and an insulating layer electrically isolating the gate electrode from the source zone, the first region, and the drain zone. The insulating layer having a step forming a first layer portion having a given thickness at the trench lower end and a second layer portion having a thickness smaller than the given thickness at the trench upper end. The first region is reinforced with the second region toward the drain zone between the trench and an adjacent trench.
Objectives of the invention are achieved by virtue of the fact that the body region is reinforced with a region of the second conduction type toward the drain zone. In order to increase the avalanche strength, the region is doped more highly than the body region.
In accordance with another feature of the invention, the region of the second conduction type, which has the same conduction type as the body region, is provided at the pn junction between the semiconductor body and the body region and has a steeper dopant gradient than the body region.
Thus, the invention""s avalanche-resistant trench MOS transistor with a deep trench and an oxide step in the trench is provided with an additional region that is introduced, preferably, by implantation and increases the electric field at the pn junction between body region and semiconductor body so that the breakdown at the pn junction takes place at a lower source-drain voltage of the MOS transistor than the breakdown at the oxide step. In such a case, the semiconductor body is preferably an epitaxial layer made of silicon applied on a semiconductor substrate made of silicon. The additional region may be buried in the body region or reach into the epitaxial layer and increase the doping concentration there in each case between trenches.
In such a case, the trench itself may, in principle, already end in the epitaxial layer of the semiconductor body or reach right into the semiconductor substrate.
Advantageously, in accordance with a further feature of the invention, it is furthermore possible to bevel the step between the insulating layer having a larger layer thickness and the insulating layer having a smaller layer thickness, thereby reducing the electric field at the step.
What is essential to the invention, then, is the introduction of an additional region of the second conduction type between the body region and semiconductor body. The region need not reach below the entire body region and also need not be outdiffused from the surface. By virtue of the additional region, which is introduced, in particular, by implantation, the breakdown voltage is not fixed as in the customary manner (cf., European Patent Application EP 0 746 030 A2, corresponding to U.S. Pat. No. 5,998,836 to Williams, U.S. Pat. No. 5,998,837 to Williams, U.S. Pat. No. 6,204,533 to Williams et al., U.S. Pat. No. 6,049,108 to Williams et al., and U.S. Pat. No. 6,140,678 to Grabowski et al.) by a smaller distance between additional doping and substrate compared with the distance between trench bottom and substrate, but by a higher doping concentration and by inclusion of the effect of the deep trenches that models the electric field. As an advantage of the invention, note is made that the additional region with the higher doping need not reach to a point below the trenches.
In accordance with an added feature of the invention, the additional region that reinforces the body region and is introduced, preferably, by ion implantation can be provided between two trenches by phototechnology and annealed, so that the doping in the actual channel region is not altered. In accordance with an additional feature of the invention, a practical embodiment may be implemented, for example, by square cells or in strip form.
Furthermore, in accordance with yet another feature of the invention, it is also possible for the additional region that reinforces the body region to be introduced in strips perpendicular to the trenches or any other desired geometric forms by implantation, for example, and annealed, so that the doping in the channel region is increased and such part of the MOS transistor no longer contributes to the channel current.
In accordance with yet a further feature of the invention, the second region is disposed at a distance between the trench and the adjacent trench and the second region is parallel to the trench and the adjacent trench.
In accordance with yet an added feature of the invention, the region runs perpendicular to the trenches.
In accordance with yet an additional feature of the invention, the region has a charge carrier concentration of between 1017 to 1019 charge carriers/cm3.
In accordance with again another feature of the invention, the body has a semiconductor substrate and an epitaxial layer on the substrate, and the trench extends into the epitaxial layer.
In accordance with again a further feature of the invention, the epitaxial layer and the substrate have a junction therebetween and the trench ends in a vicinity of the junction.
In accordance with again an added feature of the invention, the first conductivity type is a p-conductivity type.
With the objects of the invention in view, there is also provided a trench MOS transistor configuration, including a semiconductor body with a first conductivity type, the body forming at least one drain zone with the first conductivity type, the body having trenches each having a gate electrode, a trench side area, a trench upper end, and a trench lower end extending into the body, at least one source zone with the first conductivity type, the source zone disposed in the trench side area at the trench upper end and having a source lower end, at least one first region with a second conductivity type, at least one second region with the second conductivity type, the second region buried in the first region, having a higher doping than the first region, and disposed between the source zone and the drain zone, at least one insulating layer electrically isolating the gate electrode from the source zone, the first region, and the drain zone, the insulating layer having a step forming a first layer portion having a given thickness at the trench lower end and a second layer portion having a thickness smaller than the given thickness at the trench upper end, and the first region reinforced with the second region toward the drain zone between one of the trenches and an adjacent other one of the trenches.
Other features that are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a trench MOS transistor, it is, nevertheless, not intended to be limited to the details shown because various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof, will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.